1. Field of the Invention
The present invention relates to a method and an apparatus for masking a postamble ringing phenomenon in a memory device, and more particularly to a method and an apparatus for masking a phenomenon so as to avoid invalid data being written by the postamble ringing phenomenon in a write operation in a DDR SDRAM.
2. Description of the Prior Art
In general, when a write operation is performed in a DDR SDRAM, data are synchronized with a DQS signal outputted from a memory controller to be transmitted to a global input/output line in a memory device. However, when the memory controller transmits the DQS signal to the memory device, a ringing phenomenon may occur after a postamble. In this case, the memory device may write invalid data and cause an abnormal operation.
Hereinafter, the ringing phenomenon caused after the postamble will be described with reference to the following drawings.
FIG. 1 is a time chart of signal voltage levels illustrating a general postamble ringing phenomenon. In FIG. 1, “CLK” represents an exterior main clock signal applied to a DDR SDRAM. A DQS signal is a signal applied from a memory controller, and data are synchronized with a rising and a falling edge of the DQS signal and are then applied. Further, DQ represents data applied to a memory device. The time interval “tDQSS” represents a time until a rising edge of a first DQS signal occurs after a write command is applied, and the “tDQSS” is generally determined as having a value of 0.75tCK to 1.25tCK. Herein, the “tCK” represents a period of the exterior main clock signal CLK. In reference, in FIG. 1, the data DQ sequentially inputted are marked by reference numerals 1, 2, 3, and 4, and reference numerals 5 and 6 refer to invalid data which may be applied as a result of a ringing phenomenon.
In a general write operation, data 1 and 2, which are synchronized with a rising and a falling edge of the first DQS signal to be inputted, are synchronized with a time point A of the exterior main clock signal CLK to be transmitted to an input terminal of a data input/output detection amplifier Din IOSA 150 (FIG. 2). Data 3 and 4, which are synchronized with a rising and a falling edge of a second DQS signal to be inputted, are synchronized with a point B of the exterior main clock signal CLK to be transmitted to the input terminal of the data input/output detection amplifier 150.
However, as shown in FIGS. 1 and 2, when a ringing phenomenon (i.e., an unstable shift state of a DQS signal) occurs after a write postamble, a DQS buffer 100, which receives the DQS signal determines the DQS signal, which is shifted to an unstable state by the ringing phenomenon, to be a valid DQS signal. Therefore, invalid voltage levels 5 and 6 on the DQ signal are synchronized with a rising and falling edge of the DQS signal and thereby are substituted for valid data 3 and 4 stored in a data input latch Din latch 130. This causes a problem in that the invalid data 5 and 6 are undesirably synchronized with the point B of the exterior main clock signal CLK, and are then transmitted to the input terminal of the data input/output detection amplifier 150.
FIG. 2 is a block diagram of a conventional data input terminal 101 used in order to prevent the occurrence of an operation fail due to a postamble ringing phenomenon. As shown in FIG. 2, in order to prevent the ringing phenomenon from occurring, when a falling edge of the last DQS signal (shown in FIG. 1 as a falling edge of the second DQS signal) outputted from a DQS latch 110 occurs, the DQS latch 110 is disabled by means of a DQS latch control section 140 issuing a control signal “dis dsb” upon receiving the last DQS signal. Disabling the DQS latch 110 prevents the operation failure due to the ringing phenomenon.
However, this conventional method has a problem in that the method does not perform a stable write operation if tDQSS has a value of 0.75tCK to 1.25tCK. That is, in the case of the DQS falling signal, the DQS falling signal is received to disable the buffer 150, and the buffer 100 must be in a standby state before the next DQS falling signal is inputted. However, it is impossible to accurately control the timing sequence so as to cause the buffer 100 to be in a standby state before the next DQS falling signal is inputted. In some cases, the conventional method cannot completely mask a wide range of ringing phenomena that may be generated after the tDQSS having a value of 0.75tCK to 1.25tCK.
Further, when only the falling signal of a DQS buffer 100 is controlled, a timing mismatch may be generated during a rising and falling edge of the DQS signal, in comparison with the exterior main clock signal CLK. In such a case, as compared with the exterior main clock signal CLK, it is difficult to identically control the rising timing and falling timing sequences of the DQS signal as a result of variations in the process, voltage, and temperature (PVT) conditions. Accordingly, the conventional method cannot be easily employed in a memory device operating at high speeds.